1. Field of the Invention
The present invention is related to random access memories (RAMs) and more particularly to static RAM (SRAM) access timing.
2. Background Description
Integrated circuits (ICs) are commonly made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND).
A typical static random access memory (SRAM) cell is a pair of cross coupled inverters storing a single data bit. A pair of pass gates (FETs) selectively connect the complementary outputs of the cross coupled inverter to a corresponding complementary pair of bit lines. A word line connected to the gates of the pass gate FETs selects connecting the cell to the corresponding complementary pair of bit lines. Normally, an N row by M column SRAM array is organized as N word lines by M column lines. Each column line includes one or more (K) bit line pairs. Accessing Kbits (for a read or a write) from array entails driving one of the N word lines, turning on the pass gates for all M by K cells on that word line. With the pass gates on for that selected word line, the cross coupled cell inverters are coupled to the corresponding bit line pairs, partially selecting the M by K cells on that word line. Selection of one of the M columns selects the K cells on that word line, the Kbits actually being accessed. The remaining (M−1) by K bits remain partially selected during the access. During a read, each partially selected cell couples its contents to the corresponding bit line pair such that each of the bit line pairs rises/droops, usually, only to develop sufficient signal (e.g., 50 mV) for a sense amplifier. The selected K bit line pairs are coupled to a sense amplifier, which senses the contents of the selected cells from the signal on the coupled K bit line pairs. Then, after sensing data for the selected Kbits, the word line returns low again, deselecting/isolating the M by K cells on that word line.
During a write, however, the K selected bit line pairs are driven to opposite extreme voltages (Vdd and GND) or write voltages with the bit line voltages for the remaining partially selected cells being substantially the same as for a read access. With the write voltages on the selected bit line pairs and the word line high, the write voltages on the bit line pairs begin to pass through the selected cell pass gates, i.e. to the cell cross coupled inverters. Any selected cell that is being written with what it already stores, remains unchanged. Any selected cell that is in the opposite state of what is being written must be switched, which takes a minimum time depending upon the cell design and cell technology know as the cell write time. For an ideally balanced cell, it is sufficient to force the cross coupled latches just beyond the voltage mid points (i.e., to Vdd/2+δ/2 and Vdd/2−δ/2) or beyond cross over before dropping the word line and allowing the cross coupled latches to switch the rest of the way. So, once cell voltages cross over, the word line may be dropped to isolate the M by K cells from the bit line pairs and to capture the new data in the cells. Once the word line is low, the bit line pairs may be released, e.g., both of each pair driven or restored high and decoupled from the write driver.
If insufficient signal develops (i.e., <δ) in the cell, however, the data write may fail and, the cell may remain unswitched or become meta-stable. Either result is unsatisfactory and unreliable because cell contents are indeterminate. So, the write may fail, for example, if the word line drops too soon or, the bit line pair voltage change too soon, e.g., from the write driver terminating prematurely. To avoid this and insure that each write is successful, both the word line must be held high for the minimum write time and, the selected bit line pairs must be held at the write voltages at least until after the word line is returned low.
For a synchronous SRAM design, typically, word selection is a multiple of a timing period, e.g., a half cycle, chosen to meet array timing constraints. So, for a write, while the word line is selected for that multiple, i.e., at least as long as the minimum write time, a second longer timing unit (e.g., 2 timing periods or a full cycle) are required for bit and write control signals to insure that the bit line pair voltages remain stable until after the word line is unselected. This extends the write access time. Unfortunately, once sufficient additional time is added for restoring the bit lines and write driver, access cycles are considerably longer than the word line select, perhaps as much as three or four times as long. This impairs SRAM performance and performance for anything accessing the SRAM.
Thus, there is a need to reduce RAM access time.